Samsung Foundry plans to detail its second-generation 3-nm-class manufacturing technology and performance-enhanced 4-nm-class manufacturing process at its symposium on VLSI technology and circuits in Kyoto in 2023. SF3 (3GAP) promises to deliver tangible improvements for mobile and SoC, while SF4X (N4HPC) is specifically designed for the most demanding High Performance Computing (HPC) applications Therefore, both technologies are important to chip contract manufacturers.
2nd Generation 3 nm node with GAA transistors
Samsung’s upcoming SF3 (3GAP) process technology is an enhanced version of the company’s SF3E (3GAE) manufacturing process, which the company has developed for Multi-Bridge-Channel Field Effect Transistors (MBCFETs). This node promises additional process optimizations, but the foundry doesn’t want to compare He SF3 and He SF3E. Compared to its direct predecessor SF4 (4LPP, 4nm class, low power plus), SF3 claims 22% performance increase for the same power and complexity, or 34% power reduction for the same clock and transistor count doing. 21% reduction in logic area. It is unclear if the company has achieved scaling of SRAM and analog circuits.
In addition, Samsung claims that SF3 allows even greater design flexibility by varying the nanosheet (NS) channel width of MBCFET devices within the same cell type. Interestingly, variable channel width is a long-debated feature of GAA transistors, so the way Samsung is wording it in the context of his SF3 means the SF3E doesn’t support it. There is likely to be.
So far, neither the conglomerate’s chip development arm, Samsung LSI, nor any of Samsung Foundry’s other customers have officially announced a single highly complex processor mass-produced on the SF3E/3GAE process technology. . In fact, according to TrendForce, the only publicly acknowledged application to use his 3nm-class manufacturing process, an industry first, appears to be cryptocurrency mining chips. This is not particularly surprising since the use of Samsung’s “early” nodes is generally very limited.
By contrast, Samsung’s “plus” technology is typically used by a wide range of customers, so its SF3 (3GAP) process could see much higher volumes when it becomes available in 2024. I have.
SF4X for ultra-high performance applications
In addition to SF3 designed for various possible use cases, Samsung Foundry has SF4X (4HPC, 4 nm class high performance computing) are being prepared.
To deal with such a chip, Samsung’s SF4X offers a 10% performance boost and 23% power reduction. Samsung doesn’t explicitly specify the process node on which the comparison is being made, but presumably this goes against his default SF4 (4LPP) manufacturing technique. To achieve this, Samsung re-evaluated the transistor source and drain stress, then redesigned (perhaps under heavy load) and also performed transistor-level design technique co-optimization (T-DTCO). , introduced a new Middle of Line (MOL). ) schema.
With new MOL, SF4X offers a silicon-proven CPU minimum voltage (Vmin) of 60mV, 10% lower off-state current (IDDQ) variation, and high voltage (Vdd) operation above 1V without performance degradation guaranteed and improved SRAM process margins.
Samsung’s SF4X will be a rival to TSMC’s N4P and N4X nodes scheduled for 2024 and 2025 respectively. It is difficult to tell which technology offers the best combination of performance, power, transistor density, efficiency and cost based solely on the claimed specifications. That said, the SF4X will be Samsung’s first node in recent years designed specifically with HPC in mind.
